1. Field of the Invention
This invention concerns digital logic circuits and more particularly bistable circuits protected from metastability conditions in high-speed signalling environments.
2. Description of the Prior Art
In the operation of digital logic systems, externally provided binary signals are received on system input lines and, in selected combinations, applied to various logic elements within the system. Binary signals have two possible opposite direction edge-transitions between two possible steady level phases, the time order of which is the mechanism for distributing timing or data signal intelligence to elements within a logic system. Temporary values are transformed by receiving logic elements in combination with other signals to produce output signals to drive succeeding logic elements. Binary signals may be switching between the two valid levels when sampled at an instant determined by a second signal, yielding an ambiguous sample value which can cause metastability in, or otherwise impair the operation of, receiving elements. Circuit paths of various lengths and complexities impose different delays in propagating signals, making it difficult for circuit designers to ensure that signals propagating through distinct paths will arrive at specified nodes in specified sequences, and remain stable long enough for receiving elements to respond correctly. To prevent different propagation delays from causing erroneous logic states, logic systems generally control signal propagation sequences and durations by bistable memory elements or "flip-flops" employed at appropriate check points of the circuit. When stimulated by an input signal, a flip-flop samples and holds the input signal value on the flip-flop output line, until other flip-flop input signal conditions change. Signal regulation by flip-flops helps satisfy timing constraints within systems. The signal reception time uncertainty problem is assumed by the flip-flops, and largely relieved for succeeding logic elements. Avoidance of flip-flop metastability and achievement of correct system switching operation correctness depend on switching protocol and time interval constraints, and flip-flop mechanisms.
In synchronized or "locally synchronous" circuits, signal timing and switching are controlled by a central-timebase (local to the immediate surrounding circuitry) providing clock signals to enable or trigger flip-flops to sample input signals, which the flip-flops hold as output signals during a time interval to "set-up" input lines in succeeding ranks of flip-flops, in preparation for being sampled at the next clock pulse. There may also be a "hold time" requirement such that sampled input signals must not change for a brief time after the clock pulse. These set-up and hold time constraints limit synchronized circuit speed.
In contrast, there is no local or central timebase for "locally asynchronous" circuits, in which timing and data information are contained in signal sequences received from associated systems. Switching events are time-separated by minimum intervals defined for the system, and these switching events often contain implied recoverable timing information as well as data.
Logic elements controlled by a common timebase operate synchronously with respect to each other, yet operate asynchronously with respect to other logic elements not controlled by the common timebase, regardless of whether the other elements are controlled by other clocks. Signal timing control ends at the boundary of both synchronous and asynchronous systems, which must relate their timing to the timing of any relatively asynchronous transmitting circuit in order to receive signals from that transmitter. Local synchronization is subject to metastability in interfacing to other locally synchronous subsystems, or when edge-event inputs cannot be prevented from occurring simultaneously or which occur unrecoverably.
Digital subsystem signal communication can be examined wherever two subsystems interact. Maintaining the stability of logic system switching becomes more difficult as the number of independently-timed sequential logic subsystems increases. In modern systems, the tendency is to have many interacting subsystems comprising a system. Essentially, this means that the signalling synchronization loses precision and becomes more asynchronous. The totality of a system comprised of constituent subsystems may be considered to be hierarchically organized. As signals are exchanged across subsystems, various layers within a system hierarchy are stimulated.
Many digital systems include both local nodes (within a few feet), as well as possibly quite distant nodes (in spacecraft millions of miles away). Various interconnecting media such as wires, radio waves and optical carriers used within hierarchically organized systems (with complex digital subsystems) exhibit timing problems in clocked flip-flops used where subsystems exchange signals. Complex multilevel or hierarchical signalling protocols require additional decisions, and often result in increased ranking of flip-flops within the various subsystems. Hierarchical subsystem nodes are each analogous to independent locally synchronized systems as described above. Hierarchical system levels may be classified according to constraints (FIGS. 1 and 2a, 2b) upon the relative time-order alignments of the signal edges.
In "rigidly asynchronous" signalling, FIG. 1, signal edges are caused by other edges without explicit synchronization to a particular timebase, but signal edge relative alignments are constrained to be spaced over some range of time. A "granular" asynchronous signalling protocol defines how to assemble edge transition events to form intelligence-bearing signal groups, but does not necessarily dictate signal group spacings, which may be irregular.
In the FIG. 1 example of rigidly asynchronous signalling, a Sender and a Receiver exchange data packets according to a four-edge signalling protocol. The Sender signals on assertive-low request line REQ to the Receiver, and the Receiver signals on assertive-low acknowledge line ACK to the Sender. Signalling cycles 1 and 2 are made up of individual time intervals Tax, Tbx, and Tcx, which may all be different and are all larger than some minimum time and larger than 0 but also not larger than some maximum time. Ta1, Tb1, Tc1 comprise the total time interval Tcycle #1 whereas Ta2, Tb2 and Tc2 comprises the total time interval Tcycle #2. The intervals Tax, Tbx, Tcx are subject only to the aforementioned constraints which means that total time intervals of a complete cycle in general are not necessarily of equal duration yet all are separated by a time Tw greater than 0. The rigidly asynchronous constraint that signals be time-separated by minimum and/or maximum time-windows requires rapid-response flip-flops. Rigidly asynchronous signalling is used in backplane bus handshake-control protocols, serial data communications disciplines, and local area network (LAN) protocols.
Referring to FIGS. 2a and 2b, in "fully asynchronous" signalling protocols, signal edges are caused by other signal edges, undergo transitions or "recycle" no faster than at a rate Tp-1, last at least minimum times at HIGH (TpwH) and LOW (TpwL) levels, and may be assembled as defined by the protocol to form groups of intelligence-bearing signals. Fully asynchronous signalling does not constrain relative phase alignments and spacing Tbefore and Tafter of received signals relative to local signals. A given subsystem or node receives asynchronous signal edges randomly or uncontrollably, possibly coincidentally with receipt of local synchronizing signals, and may jitter around edges in a local synchronizing signal.
Fully asynchronous signalling is illustrated in the FIG. 2a example of received signal synchronization. A constant-frequency timebase "Synch" clock samples "Asynch" data signals, in which edge-event times are not constrained. FIG. 2b illustrates arbitration of which is first between two fully asynchronous negative edge Request lines, REQ1 and REQ2. Each Request line is constrained according to the rigidly asynchronous protocol, but two or more request lines acting simultaneously upon a single element encounters the problems of how relatively to compare the two signal edges,.and what to do if the two signal edges appear simultaneously. Arbitration is an implicitly edge-driven hierarchy, in which one signal edge-event is weighed over another, requiring flip-flops to be sensitive to possibly very brief intervals approaching or even equaling zero between edge-events. The relative timing or alignment of active phases of signals can cause conventional flip-flops to miss signal edges, produce insufficiently wide output pulses, or succumb to metastability.
Fully asynchronous signalling is applied in interrupt and direct memory access (DMA) requesters and signal synchronizers in communication and backplane buses; in timing recovery circuits in magnetic or optical storage media; and in digital edge-based phase comparators.
To contend with metastable conditions caused by input signal values changing or conflicting at the moment of sampling, some conventional flip-flops stabilize metastable values between an input stage and an output stage. In a master-slave flip-flop, a clock signal enables an input master stage to produce an intermediate signal, in which possible metastable values are expected to settle before the intermediate signal is transferred to an output slave stage when the slave is enabled (by a subsequent phase of the clock). However, delaying metastable intermediate signals between stages does not guarantee that by the end of a finite delay metastable conditions will be resolved.
U.S. Pat. No. 4,398,105 discloses a flip-flop arbiter circuit in which input stage intermediate output signals having metastable values are detected by a difference detector which disables an output stage from passing the intermediate signals until metastable values have settled.
Using sequential circuits to combine multiple signals into an input signal and to stabilize the input signal value before applying the input signal to a flip-flop delays the flip-flop response to the multiple signals. U.S. Pat. No. 3,917,961 reduces this delay by using separate master-input stages to receive and stabilize each input signal, and by combining the master-stage outputs in a wired OR connection to produce an intermediate signal for application to a single slave-output stage. However, conflicting outputs from the master stage can still cause a metastable intermediate signal, which may be transferred through the slave stage to the flip-flop output line.
U.S. Pat. No. 4,045,693 discloses an RS flip-flop with output lines fed back through an input network to block redundant input signals from reasserting the existing state of the flip-flop, and to pass an input signal edge asserting the alternate state. However, this does not relieve the problem of an input signal changing just as the input network enables the input, causing metastability in the flip-flop.
In both rigidly and fully asynchronous signalling environments, the problems of using flip-flops for signal synchronization, arbitration, and backplane bus timing and protocol logic requires stable circuit operation without adding excessive logic elements for reception of edge-events. Several constraints result from these needs. Sufficient timing margins must be ensured, susceptibility to metastability-causing events must be minimized or avoided, important edge-events cannot be missed, and nodes internal to a system element should not generate spurious or insufficiently narrow pulses. These problems establish a need for an architecture for bistable devices to respond to asynchronous signal events more quickly, with fewer time constraints than previous architectures, and with improved predictability in a variety of edge event stimuli.